Process and Device Technologies for High Speed Self-Aligned Bipolar Transistors

Tohru NAKAMURA  Takeo SHIBA  Takahiro ONAI  Takashi UCHINO  Yukihiro KIYOTA  Katsuyoshi WASHIO  Noriyuki HOMMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.9   pp.1154-1164
Publication Date: 1995/09/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category: 
Keyword: 
silicon bipolar,  double polysilicon,  high speed,  self-alignment,  

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Summary: 
Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.