IEICE Trans - 3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer

3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer

Kimio UEDA
Nagisa SASAKI
Hisayasu SATO
Shunji KUBO
Koichiro MASHIKO

Publication
IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.866-872
Publication Date: 1995/07/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword:
multiplexer, demultiplexer, silicon-bipolar, low-power, ECL,

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Summary:
This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).