BIST Circuit Macro Using Microprogram ROM for LSI Memories

Hiroki KOIKE  Toshio TAKESHIMA  Masahide TAKADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.7   pp.838-844
Publication Date: 1995/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
memory,  BIST,  ROM,  tester,  macro,  

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Summary: 
We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and VOH/VOL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.