Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme

Hiroshi SUGAWARA  Toshio TAKESHIMA  Hiroshi TAKADA  Yoshiaki S. HISAMUNE  Kohji KANAMORI  Takeshi OKAZAWA  Tatsunori MUROTANI  Isao SASAKI  

IEICE TRANSACTIONS on Electronics   Vol.E78-C    No.7    pp.825-831
Publication Date: 1995/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
flash memory,  64 Mbit,  multi-bit programming,  data register,  hierarchical,  

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A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.