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A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
flash memory, NAND, folded bit line verify read, charge pump,
Full Text: PDF(529.3KB)>>
An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.