A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture

Hiromi NOBUKATA  Kenichi SATORI  Shinji HIRAMATSU  Hideki ARAKAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.7   pp.818-824
Publication Date: 1995/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory,  NAND,  folded bit line verify read,  charge pump,  

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Summary: 
An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.