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Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
SOI, SIMOX, SRAM, low-voltage operation, back-gate bias effect,
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The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The Vt shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.