PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs

Kazuyuki NAKAMURA  Shigeru KUHARA  Thoru KIMURA  Masahide TAKADA  Hisamitsu SUZUKI  Hiroshi YOSHIDA  Tohru YAMAZAKI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.7   pp.805-811
Publication Date: 1995/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 


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Summary: 
PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.