IEICE Trans - A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits

A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits

Suguru TACHIBANA Hisayuki HIGUCHI Koichi TAKASUGI Katsuro SASAKI Toshiaki YAMANAKA Yoshinobu NAKAGOME

Publication
IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.735-738
Publication Date: 1995/06/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
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Summary:
The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-µm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns.