IEICE Trans - Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design

Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design

Masato MOTOMURA Toshiaki INOUE Hachiro YAMADA Akihiko KONAGAYA

Publication
IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.623-630
Publication Date: 1995/06/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
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Summary:
This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 µm CMOS design rule.