Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization

Masaaki YAMADA  Sachiko KUROSAWA  Reiko NOJIMA  Naohito KOJIMA  Takashi MITSUHASHI  Nobuyuki GOTO  

IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.4   pp.441-446
Publication Date: 1995/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
LSI,  layout,  transistor sizing,  low power,  CAD,  

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The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.