A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability

Kunihiro ASADA  Junichi AKITA  

IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.4   pp.436-440
Publication Date: 1995/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
charge and discharge power,  probability parameter,  finite state machine,  signal assignment,  output probability,  

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Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.