For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
Hiroyuki YAMAUCHI Hironori AKAMATSU Tsutomu FUJITA
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
charge-recycling, low-power, bus-architecture, small-swing, ultra-high-data-rate,
Full Text: PDF(1001.8KB)>>
A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at Vcc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.