High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS

Kunihiro SUZUKI  Tetsu TANAKA  Yoshiharu TOSAKA  Hiroshi HORIE  Toshihiro SUGII  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.4   pp.360-367
Publication Date: 1995/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Device Technology
Keyword: 
MOSFET,  SOI,  double-gate,  high-speed,  low-power,  threshold voltage,  

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Summary: 
We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.