0.15 µm CMOS Devices with Reduced Junction Capacitance

Akira TANABE  Kiyoshi TAKEUCHI  Toyoji YAMAMOTO  Takeo MATSUKI  Takemitsu KUNIO  Masao FUKUMA  Ken NAKAJIMA  Naoki AIZAKI  Hidenobu MIYAMOTO  Eiji IKAWA  

IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.3   pp.267-273
Publication Date: 1995/03/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
CMOS,  EB lithography,  Ti salicide,  SPICE,  

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0.15 µm CMOS transistors have been fabricated. TiSi2 salicide was used for the gate electrode and source/drain to reduce parasitic resistance. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduce the junction capacitance, a reasonably short ring oscillator delay of 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution on the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effective for scaling the delay time and power consumption, because the source/drain size difficult to scale down to as small as the gate length.