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Temperature Compensated Piezoresistor Fabricated by High Energy Ion Implantation
Takahiro NISHIMOTO Shuichi SHOJI Kazuyuki MINAMI Masayoshi ESASHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/02/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Micromachines and Micro Electro Mechanical Systems)
piezoresistor, ion implantation, temperature compensation, JFET,
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We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.