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ULSI Realization of MPEG2 Realtime Video Encoder and Decoder--An Overview
Masahiko YOSHIMOTO Shin-ichi NAKAGAWA Tetsuya MATSUMURA Kazuya ISHIHARA Shin-ichi URAMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
video compression/decompression, video encoder, video decoder, MPEG2, video signal processor,
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This paper will describe an overview on several design issues and solutions for the realization of MPEG2 encoder &decoder LSIs. ULSI technology and video-coding specific design have been able to actualize an MPEG2 encoder &decoder LSI with realtime capability, flexibility and cost effectiveness, though MPEG2 processing at MP＠ML (Main Profile and Main Level) requires an enormous computation power of 10-200 GOPS depending on the motion estimation algorithm and a search range. Video coding processors, whose performance has been enhanced at the rate of one order per 3 years, have reached the performance level required to implement MPEG2 encoding using multiple chip configuration. This has been achieved by a hybrid architecture with video-oriented RISC and hardware engine optimized for coding algorithms. Intensive circuit optimization was carried out for transform coding such as DCT and predictive coding with motion estimation. Now cost effective MPEG2 decoders have begun to penetrate the multimedia market. There are two main design issues. One is the architectural and circuit design which minimizes the silicon area and power dissipation. The other is external DRAM control which makes use of DRAM storage and band width efficiently to reduce the system cost. Also future trends in a deep submicron era will be discussed. A single chip MPEG2 MP＠ML encoder is expected to appear in the 0.25 micron era at the latest. An MPEG2 MP＠ML decoder could be compressed to an area of about 25 mm2.