An Instruction Set Optimization Algorithm for Pipelined ASIPs

Nguyen Ngoc BINH  Masaharu IMAI  Akichika SHIOMI  Nobuyuki HIKICHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E78-A   No.12   pp.1707-1714
Publication Date: 1995/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
ASIP,  pipelined architecture,  HW/SW partitioning,  performance estimation,  PEAS-I system,  

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This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.