"FASTOOL" an FIR Filter Compiler Based on the Automatic Design of the Multi-Input-Adder

Takao YAMAZAKI  Yoshihito KONDO  Sayuri IGOTA  Seiichiro IWASE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E78-A   No.12   pp.1699-1706
Publication Date: 1995/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FIR filter,  filter compiler,  multi-input-adder,  HDL-design environment,  Verilog-HDL,  

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Summary: 
We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.