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A Bipolar-Based 0.5 µm BiCMOS Technology on Bonded SOI for High-Speed LSIs
Makoto YOSHIDA Toshiro HIRAMOTO Tsuyoshi FUJIWARA Takashi HASHIMOTO Tetsuya MURAYA Shigeharu MURATA Kunihiko WATANABE Nobuo TAMBA Takahide IKEDA
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: General Technology
BiCMOS, bonded SOI, double polysilicon bipolar, trench isolation, stress,
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A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.