Low-Voltage and Low-Power ULSI Circuit Techniques

Masakazu AOKI  Kiyoo ITOH  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.8   pp.1351-1360
Publication Date: 1994/08/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: General Technology
battery operation,  subthreshold current,  switched power-line scheme,  self-reverse biasing,  switched source impedance,  hierarchical power line,  partial activation of circuit blocks,  charge recycle,  reference-voltage generator,  

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Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.