A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme

Hisashi IWAMOTO  Naoya WATANABE  Akira YAMAZAKI  Seiji SAWADA  Yasumitsu MURAI  Yasuhiro KONISHI  Hiroshi ITOH  Masaki KUMANOYA  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.8   pp.1328-1333
Publication Date: 1994/08/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
synchronous DRAM,  SDRAM,  high speed DRAM,  multiple-register,  

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A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.