A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs

Tadahiko SUGIBAYASHI
Isao NARITAKE
Hiroshi TAKADA
Ken INOUE
Ichiro YAMAMOTO
Tatsuya MATANO
Mamoru FUJITA
Yoshiharu AIMOTO
Toshio TAKESHIMA
Satoshi UTSUGI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C    No.8    pp.1323-1327
Publication Date: 1994/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memory,  DRAM,  test,  

Full Text: PDF>>
Buy this Article



Summary: 
A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.