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PATDRAM: Pixel-Aligned Triple-Port DRAM
Toshiki MORI Tetsuyuki FUKUSHIMA Akifumi KAWAHARA Katsumi WADA Akihiro MATSUMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
video memory, multi-port DRAM, graphics, multimedia,
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This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Triple-port DRAM (PATDRAM). The PATDRAM has a 270 K word 16 b Random Access Memory (RAM), a 512 word 8 b Serial Access Memory-(a) (SAMa) and a 1024 word 4 b Serial Access Memory-(b) (SAMb). The random port, serial-a and serial-b port can be operated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerates graphics performance and simplifies in multimedia systems which manage both realtime video and computer graphics data, and also accelerates graphics performance in both two-dimensional (2D) and three-dimensional (3D) graphics systems. PATDRAM was designed using a 0.6 µ double metal, triple poly, stacked capacitor, CMOS process technology in a 10.98 mm9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transfer mask register and 5 Kgate logic.