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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
DRAM, memory bottleneck, data bandwidth, latency, synchronous DRAM, pipeline architecture, data prefetching, cache DRAM, fast copyback, Rambus interface, Rambus DRAM, protocol packet, PLL,
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The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.