Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs

Yoshichika FUJIOKA  Michitaka KAMEYAMA  Nobuhiro TOMABECHI  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.7   pp.1123-1130
Publication Date: 1994/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
delay time,  multi-operand multiply-addition,  reconfiguration,  digital control,  FPGA,  

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In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custom VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration cotrol computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 µs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).