Design of a CAM-Based Collision Detection VLSI Processor for Robotics

Masanori HARIYAMA  Michitaka KANEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.7   pp.1108-1115
Publication Date: 1994/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
special-purpose VLSI,  content-addressable memory (CAM),  rectangular solid representation,  CORDIC algorithms,  

Full Text: PDF>>
Buy this Article

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.