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Quantizer Neuron Chip (QNC) with Multichip Extendable Architecture

Masakatsu MARUYAMA  Hiroyuki NAKAHIRA  Shiro SAKIYAMA  Toshiyuki KOHDA  Susumu MARUNO  Yasuharu SHIMEKI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.7   pp.1057-1064
Publication Date: 1994/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
neural network,  neuron chip,  quantizer neuron,  recognition,  

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Summary: 
This paper discusses a digital neuroprocessor named Quantizer Neuron Chip (QNC) employing the Quantizer Neuron model and two newly developed schemes; "concurrent processing of quantizer neuron" and "removal of ineffective calculations". QNC simulates neural networks named the Multi-Functional Layered Network (MFLN) with 64 output neurons, 4672 quantizer neurons and two million synaptic weights and can be used for character or image recognition and learning. The processing speed of the chip achieved 1.6 µseconds per output neuron for recognition and 20 million connections updated per second (MCUPS) for learning. In addition, QNC can execute multichip operation for increasing the size of networks. We applied QNC to handwritten numeral recognition and realized high speed recognition and learning. QNC is implemented in a 1.2 µm double metal CMOS with sea of gates' technology and contains 27,000 gates on a 10.9910.93 mm2 chip.