A 40-mW 55 Mb/s CMOS Equalizer for Use in Magnetic Storage Read Channels

Patrick K. D. PAI  Asad A. ABIDI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.5   pp.819-829
Publication Date: 1994/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 


Full Text: PDF(979.7KB)>>
Buy this Article




Summary: 
A monolithic active equalizer in 2-µm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations.