A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation

Shigeru ATSUMI  Masao KURIYAMA  Akira UMEZAWA  Hironori BANBA  Kiyomi NARUKE  Seiji YAMADA  Yoichi OHSHIMA  Masamitsu OSHIKIRI  Yohei HIURA  Tomoko YAMANE  Kuniyoshi YOSHIKAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.5   pp.791-799
Publication Date: 1994/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
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Summary: 
A 16-Mb flash EEPROM has been developed based on the 0.6-µm triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 µm1.7 µm, and the die size has resulted in 7.7 mm17.32 mm.