Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory

Shin-ichi KOBAYASHI  Hiroaki NAKAI  Yuichi KUNORI  Takeshi NAKAYAMA  Yoshikazu MIYAWAKI  Yasushi TERADA  Hiroshi ONODA  Natsuo AJIKA  Masahiro HATANAKA  Hirokazu MIYOSHI  Tsutomu YOSHIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.5   pp.784-790
Publication Date: 1994/05/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 µm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.81.6 µm2 and the chip measures 5.85.0 mm2. The divided bit line structure realizes a small NOR type memory cell.