Sub-1-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM's

Hitoshi TANAKA
Yoshinobu NAKAGOME
Masakazu AOKI

IEICE TRANSACTIONS on Electronics   Vol.E77-C    No.5    pp.778-783
Publication Date: 1994/05/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 Vp-p Vcc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.