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A 1.5-ns Cycle-Time 18-kb Pseudo-Dual-Port RAM with 9K Logic Gates
Masato IWABUCHI Masami USAMI Masamori KASHIYAMA Takashi OOMORI Shigeharu MURATA Toshiro HIRAMOTO Takashi HASHIMOTO Yasuhiro NAKAJIMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
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An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing α-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.52 µm2 and the chip size is 1111 mm2.