A 110-MHz/1-Mb Synchronous TagRAM

Yasuo UNEKAWA  Tsuguo KOBAYASHI  Tsukasa SHIROTORI  Yukihiro FUJIMOTO  Takayoshi SHIMAZAWA  Kazutaka NOGAMI  Takehiko NAKAO  Kazuhiro SAWADA  Masataka MATSUI  Takayasu SAKURAI  Man Kit TANG  William A. HUFFMAN  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.5   pp.733-740
Publication Date: 1994/05/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

Full Text: PDF(743.6KB)>>
Buy this Article

A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-µm double polysilicon double-metal BiCMOS technology.