A 120-MHz BiCMOS Superscalar RISC Processor

Shigeya TANAKA
Takashi HOTTA
Fumio MURABAYASHI
Hiromichi YAMADA
Shoji YOSHIDA
Kotaro SHIMAMURA
Koyo KATSURA
Tadaaki BANDOH
Koichi IKEDA
Kenji MATSUBARA
Kouji SAITOU
Tetsuo NAKANO
Teruhisa SHIMIZU
Ryuichi SATOMURA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C    No.5    pp.719-726
Publication Date: 1994/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
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Summary: 
A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm16.5 mm, and utilizes 3.3 V/0.5 µm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.