4-2 Compressor with Complementary Pass-Transistor Logic

Youji KANIE  Yasushi KUBOTA  Shinji TOYOYAMA  Yasuaki IWASE  Shuhei TSUCHIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.4   pp.647-649
Publication Date: 1994/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 
electronic circuits,  multiplier,  regularly structured Wallace tree,  4-2 compressor,  complementary pass-transistor logic,  

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Summary: 
This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.