Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)

Kyoung-Rok CHO  Kazuma OKURA  Kunihiro ASADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.4   pp.615-623
Publication Date: 1994/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
completion signal,  asynchronous microprocessor,  self-timed data path,  DCVSL,  

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Summary: 
This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.