For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
Kyoung-Rok CHO Kazuma OKURA Kunihiro ASADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
completion signal, asynchronous microprocessor, self-timed data path, DCVSL,
Full Text: PDF>>
This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with 0.5 µm CMOS technology.