Ti Salicide Process for Subquarter-Micron CMOS Devices

Ken-ichi GOTO  Tatsuya YAMAZAKI  Yasuo NARA  Tetsu FUKANO  Toshihiro SUGII  Yoshihiro ARIMOTO  Takashi ITO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.3   pp.480-485
Publication Date: 1994/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Process Technology
Keyword: 
Ti,  TiSi2,  salicide,  subquarter-micron CMOS,  gate resistance,  

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Summary: 
Using Ti self-aligned silicide (salicide) process, we fabricated subquarter-micron complementary metal-oxide semiconductor (CMOS) devices, and studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 µm long and 10 µm wide. In the gates less than 0.1 µm long, we found that agglomeration of TiSi2 takes place during low temperature annealing at 675 for 30 seconds leading to discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly increases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals that the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800 for 30 seconds, while it does not occur in TiSi2 gates less than 5 µm long. From these results we found that the gate sheet resistance can not be reduced to less than 5 Ω/sq by conventional Ti salicide technology in gates shorter than 0.4 µm due to increase in gate resistance caused by agglomeration and lack of phase transition.