Design Rule Relaxation Approach for High-Density DRAMs

Takanori SAEKI  Eiichiro KAKEHASHI  Hidemitu MORI  Hiroki KOGA  Kenji NODA  Mamoru FUJITA  Hiroshi SUGAWARA  Kyoichi NAGATA  Shozo NISHIMOTO  Tatsunori MUROTANI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.3   pp.406-415
Publication Date: 1994/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAM,  design rule,  close packed cell array,  Boosted Dual Word-Line scheme,  

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Summary: 
A design rule relaxation approach is one of the most important requirements for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high density DRAMs with the minimum development of a scaled-down MOS structure and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-line cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 times wider isolation width. The Boosted Dual Word-Line scheme provides 2n times wider 1st Al pitch on memory cell array, double word-line driver pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line scheme provides several times depth of focus (DOF) for 1st Al wiring which gives several times higher storage node and larger capacitance for capacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.91.8 µm2 memory cell.