LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs

Junji HIRASE  Takashi HORI  Yoshinori ODAKE  

IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.3   pp.350-354
Publication Date: 1994/03/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
MOSFET,  LDD,  n--gate overlap,  circuit speed,  hot-carrier-induced degradation,  

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This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.