High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application


IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.12   pp.1944-1950
Publication Date: 1994/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
I/O,  interface,  termination,  CTT,  

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High performance I/O circuits for fast memory devices such as Synchronous DRAMs were studied. For a TTL interface, the effect of capacitive loading must increase as I/O speed is increased, and signal termination is required for frequencies over 100 MHz. For this reason, industry-proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices. The results showed that open-drain type drivers have a problem; as the frequency increases, the high-level output voltage becomes degraded. In contrast, a push-pull driver T-LVTTL (Terminated Low Voltage TTL), developed as an implementation of the CTT interface specification, was found to be suitable for high-speed data transfer. A high-speed bus driver circuit connecting an impedance element in series to the stub is proposed as an application of T-LVTTL. Simulated results showed that this scheme greatly improves the signal integrity of memory bus systems; the operating frequency could very well be the highest among several schemes discussed as candidates for the post-LVTTL standard interface.