2.7 mm2 and consumes 350 mW." />

A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter

Shoichiro TADA

IEICE TRANSACTIONS on Electronics   Vol.E77-C    No.12    pp.1903-1911
Publication Date: 1994/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Analog LSIs
analog,  data converter,  A/D converter,  video,  Bi-CMOS,  sample and hold,  interpolation,  high speed,  high resolution,  comparator,  differential amplifier,  multi-stage,  mixed signal,  

Full Text: PDF>>
Buy this Article

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.