Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--

Katsuhiko KAWAZOE
Shunji HONDA
Shuzo KATO

IEICE TRANSACTIONS on Electronics   Vol.E77-C    No.12    pp.1888-1894
Publication Date: 1994/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
FEC,  Viterbi decoding,  convolutional encoding,  VLSIC,  satellite communication systems,  

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An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.