3-D CG Media Chip: An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics

Takao WATANABE  Kazushige AYUKAWA  Yoshinobu NAKAGOME  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.12   pp.1881-1887
Publication Date: 1994/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
media chip,  DRAM,  3-D computer graphics,  1.5-V operation,  0.35-µm CMOS design rule,  

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Summary: 
A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.