An Efficient Self-Timed Queue Architecture for ATM Switch LSIs

Harufusa KONDOH  Hideaki YAMANAKA  Masahiko ISHIWAKI  Yoshio MATSUDA  Masao NAKAYA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E77-C   No.12   pp.1865-1872
Publication Date: 1994/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
ATM,  ATM switch,  LSI,  self-timed systems,  

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Summary: 
A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.