High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters

Kyousiro SEKI

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A    No.6    pp.944-949
Publication Date: 1994/06/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Digital Signal Processing
state-space digital filter,  multiprocessor implementation,  block-state realization,  distributed arithmetic,  

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This paper proposes high-performance multiprocessor implementation for real-time one-dimensional (1-D) statespace digital filters (SSDFs). The block-state realization of SSDFs (BSRDF) is suitable for their high speed realization and gives the characteristics of high accuracy. Previously we proposed a VLSI-oriented highly parallel architecture for BSRDF. For the purpose of speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends only on word length, is applied to this architecture. It is implemented as a 2-D SIMD processor array, and the processor consists of n homogeneous processing elements (PEs), n being filter order. The high sampling rate of one or more hundred MHz becomes possible for high filter order. Moreover, the number of I/O data per processor can be a small fixed value for any filter order, and the number of gates can also be smaller than that in the case of using multiplier. Consequently, this proposed system can be implemented easily even in the present VLSI environment.