A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs

Ikuo HARADA  Yuichiro TAKEI  Hitoshi KITAZAWA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A   No.12   pp.2058-2066
Publication Date: 1994/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routing,  timing driven layout,  bipolar LSI,  delay model,  routing graph,  critical path,  

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Summary: 
A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.