A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout

Tetsushi KOIDE  Yoshinori KATSURA  Katsumi YAMATANI  Shin'ichi WAKABAYASHI  Noriyoshi YOSHIDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A   No.12   pp.2053-2057
Publication Date: 1994/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layout,  floorplanning,  relative placement,  topological constraint,  strong respect,  tentative insertion,  block reshaping,  

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Summary: 
This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.