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A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
sequential circuit, test generation, design for testability, scan circuit, reduced scan shift,
Full Text: PDF(625.9KB)>>
This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.