Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns

Enrico MACII  Qing XU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A   No.11   pp.1977-1979
Publication Date: 1994/11/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Computer Aided Design (CAD)
CMOS circuit,  stuck–open fault,  test generation,  

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Transistor stuck–open faults in CMOS devices are such that they force combinational circuits to exhibit sequential behaviors. It has been proved that, in general, stuck–open faults can not be modeled as stuck–at faults and, therefore, a sequence of two consecutive test vectors is necessary to guarantee stuck–open fault detection. In this paper we propose a technique to modify CMOS circuits in such a way that any stuck–open fault in the circuit can be detected using only a single test pattern. The amount of additional logic required to achieve the goal is rather limited: Two pass transistors, one input line, and one inverter (or buffer) at the output of the circuit are sufficient to make stuck–open faults detectable by test patterns generated by usual stuck–at fault test generators.