Experiments with Power Optimization in Gate Sizing

Guangqiu CHEN  Hidetoshi ONODERA  Keikichi TAMARU  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A   No.11   pp.1913-1916
Publication Date: 1994/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
low power design,  power dissipation,  gate sizing,  area–power–delay tradeoff,  

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Summary: 
In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delar and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area–power–delay tradeoff in the gate sizing procedure.